This invention relates to electronic inverters and more particularly to circuits for controlling power pole switching in such inverters.
Pulse width modulated DC to AC inverters approximate sine wave outputs by switching power pole switches at a rate higher than the fundamental sine wave frequency. In the design of pulse width modulated DC to AC inverters, it is desirable to switch the power stage in a manner which reduces certain harmonics to low values so as to ease the burden of filtering the output power to obtain a sinusoidal voltage wave. Fairly small errors in switching times can produce harmonic voltages many times greater than desired. This usually results in the use of a circuit filter which is made considerably larger than theoretically necessary to suppress these harmonics.
In a transistor inverter, for example, it is necessary to provide an underlap condition to prevent shoot-through during the switching operation. This means that to switch an output point from one polarity to another, there must be a delay after the conducting transistor is turned off, to be sure it is no longer conducting, before a complementary transistor is turned on. Many times load conditions are such that the second transistor does not conduct at all since load current is shunted through a commutating diode, thereby shortening the switching time to that of the transistor turn off time. Thus the switching time is quite variable depending on the instantaneous load current as well as the transistor turn off characteristic. Therefore, the prescribed switching schedule is not met, resulting in unpredicted harmonics.
The transistors in DC link inverters require a finite time to turn off. Depending upon the design of the base drive circuit and the current level being switched, the turn off time in typical inverters may be as long as 20 microseconds. This time is nearly proportional to the transistor current when current coupled feedback transformer base drive circuits are used. As a result, the actual output voltage pattern of a DC link inverter may vary from the programmed pattern by nearly 20 microseconds depending upon the load and power factor. This timing variation causes distortion in the output voltage. For example, an inverter with a theoretical total harmonic distortion of less than 2% was observed to have an actual total harmonic distortion greater than 8% due to this effect.
Another effect of the transistor turn off time appears at higher power levels. Increasing the power level at the same output voltage requires increased current ratings of the transistor switches and output filters. The variation of turn off time with current, however, remains approximately the same (about 5 microseconds per 100 amperes). This variation means that a transistor providing high current to the inverter output takes longer to switch and the output voltage stays high longer. That is, more output current produces more output voltage. This is a negative resistance effect. For stable operation of the inverter, the negative resistance must be balanced by real, positive resistance in the output filter and wiring. At higher power levels, this positive resistance is designed to be as small as possible, to minimize power losses and maintain high efficiency. Therefore, a power level can be reached where the net resistance is negative and the inverter output becomes unstable. This instability appears as a large current circulating in the output filter at its resonant frequency when the inverter operates at no load.
Switching time correction circuits have been developed to individually correct each switching edge using phase locked loop techniques. Such circuits are disclosed in U.S. Pat. Nos. 4,443,842; 4,502,105 and 4,504,899. Although the methods disclosed in those patents work very well under steady state conditions, they cannot respond to rapidly changing currents produced by negative resistance effects. An additional circuit is needed to eliminate the negative resistance effect.